1. Field of the Invention
The present invention relates to a semiconductor element and a semiconductor device.
2. Description of the Related Art
MOSFETs (metal-oxide-semiconductor field effect transistors) are normally placed in an off-state to prevent currents from leaking by means of pn junctions. The primary causes of leak currents include subthreshold currents and reversed carrier recombination. Such currents are small but not negligible; they determine the data holding time of DRAMs (dynamic random access memories) and define their refresh cycles. Schemes proposed so far to minimize leak currents include the reduction of crystal defects with wafers subject to epitaxial growth, and complete depletion in the off-state by use of SOI (silicon on insulator) wafers.
There has been proposed a memory element structure called gain cells capable of operating as DRAM cells with reduced stored charges. The proposed structure involves electrically charging a memory node via a write transistor so that the stored charge in the node causes a separately provided read transistor to vary its threshold voltage, which represents a piece of data stored. Related conventional techniques include a structure using polycrystal silicon for write transistors as disclosed by H. Shichijo et al., Conference on Solid State Device and Materials, pp. 265-268, 1984; and a structure using polycrystal silicon for read transistors as proposed by S. Shukuri et al., IEEE International Electron Devices Meeting, pp. 1006-1008, 1992.
Other conventional techniques related to this invention include a single electronic memory utilizing polycrystal silicon as depicted by K. Yano et al., IEEE International Electron Devices Meeting, pp. 541-544, 1993, as well as by Ishii et at., IEEE International Solid-State Circuits Conferences, pp. 266-267, 1996. In the proposed electronic memory, polycrystal silicon thin films are used concurrently to form channels as current paths and storage regions for capturing electrons. A piece of data is retained when electrons captured by a storage region change the latter's threshold voltage. What characterizes this technique is that a few electrons are enough to store one bit of data. Electrons are injected into a given storage region by applying a voltage of 12 V through 15 V to a gate electrode. To discharge the stored electrons requires applying a voltage of −10 V through −15 V to the gate electrode. The use of polycrystal silicon grains permits formation of a structure effectively smaller than the fabricated size. Memory elements in this structure are capable of operating at room temperature. A single transistor constitutes each memory element.
One of the guides to MOSFET micro-fabrication is the scaling law. According to this principle, reduction of the size to 1/K requires multiplying the substrate density by a factor of K. However, raising the substrate density narrows the depletion layer width and increases leaks from junctions. A solution to this problem involves the use of an SOI substrate for a complete depletion in the off-state. In that case, leak currents sill flow illustratively because of the reversed carrier recombination, although the currents are smaller than in ordinary substrates. At very advanced levels of micro-fabrication, uneven positions of impurities in channels can trigger the flow of leak currents. Efforts to design for a high threshold voltage can be defeated by a current path being formed at a voltage lower than the threshold voltage due to the uneven presence of impurities, with the current path condoning a flow of leak currents.
Ever-finer structures of memory cells in DRAMs, flash memories and other types of memories have translated into smaller memory cell areas than ever before. The trend has made it possible to implement ever-greater memory capacities. In particular, DRAMs with one transistor and one capacitor making up their basic structure have gained widespread acceptance as a memory device offering both high-speed performance and high degrees of integration. The growing scale of memories, however, requires longer refresh cycles. The trend thus presents a need for a low-leak FET structure. For the DRAMs, a simple-minded drive for more advanced micro-fabrication aimed at smaller memory cell areas entails narrowing areas of capacitors, reducing capacitance values of the capacitors and lowering their stored charges. Meanwhile, data lines are generally extended as the memory size increases. Since the data lines are subject to charging and discharging operations and should also be resistant to noise, the amount of stored charges cannot be too low. Hence the problem of having to devise for each new generation of DRAMs a novel scheme for building a three-dimensional capacitor structure or for enhancing the dielectric constant of capacitor insulating films.
One solution to the above problem is not directly to charge or discharge the data lines using cumulative charges but to accumulate electrical charges near transistor channels so as to vary the threshold voltage of transistors for data storage. Because the solution allows the data lines to be charged and discharged using drain currents of transistors, the problem above is bypassed and memory elements are easily reduced in size. The conventional three-transistor type DRAM has been proposed on the basis of the solution above. The three-transistor type DRAM needs to make its refresh cycle shorter than before because its amount of cumulative charges is smaller than in ordinary DRAMs. The refresh cycle is required to be shortened progressively the higher the degree of integration. This, it can be expected, will eventually result in another problem.
The EEPROM and flash memory are other memory elements that have electrical charges stored in the vicinity of transistor channels to vary the transistor threshold voltage for data retention. In operation, a high voltage is applied to a tunnel insulating film in order to inject electrons or holes into a floating gate. One disadvantage of this type of memory is that it takes time to write or read data because currents are made to flow through the insulating films. Since the operating voltage is high, it is necessary to prepare peripheral circuits of high dielectric strengths. Such peripheral circuits tend to occupy wider areas. In order to ensure reliable data retention under high-voltage application, the tunnel insulating film must at least have a thickness of a little less than 10 nm. That means the tunnel insulating film cannot be made thinner than that size while the elements are being scaled down, so that the short channel effect is getting more and more pronounced. Furthermore, the amount of currents flowing through tunnels varies considerably depending on the insulating film thickness and on the presence or absence of traps. This leads to significant variations in characteristics between memory elements.
It is therefore an object of the present invention to provide a semiconductor element operating on a threshold voltage controlling method not resorting to low leaks or to impurity injection; a scaled-down semiconductor memory device which uses such semiconductor elements and is capable of ensuring a sufficiently long refresh cycle for high-speed write operations; and a semiconductor device comprising such elements.